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TH6503
USB Low-Speed Interface
Description
The TH6503 is an integrated circuit which enables the Universal Serial Bus (USB) to be connected to a microcontroller. The interface module contains all the components required to transmit data via the USB. The TH6503 has been developed for applications requiring a low speed interface to the USB. Any microcontroller can be used for control purposes. In addition to the default endpoint 0 for control transfer up to two endpoints can be supported by TH6503. The TH6503 has been developed in conformity with USB Specifications 1.1.
Features
? Complient with USB Specification 1.1
? Supports up to three programmable endpoints for interrupt and control transfer in each direction ? Integrated oscillator for clock generation, supports 6 MHz quartz, ceramic resonator ? Data transfer at USB low speed or external clock input ? Supports suspend mode ? Simple external circuitry ? Universal serial microcontroller interface ? Register programmable ? Programmable 1.5 MHz to 6 MHz out clock for microcontroller
? Provides power supply for the microcontroller (3.3 volts or 5 volts)
TH6503 Sample Application
TH6503
Serial Interface
to USB Host / Hub
USB Interface OCLK /ORST
Microcontroller/ Customer Application
Figure 1. Typical TH6503 Sample Application Figure 1 demonstrates a typical TH6503 application. The TH6503 translates the data and control signals received from the USB in a serial format which can be read by the microcontroller. The data is stored in a FIFO buffer and can be called up from a standard microcontroller via a register programmable serial interface at any time and processed further. Data generated by peripheries is passed to the TH6503 with the same protocol and stored in a FIFO buffer until it is collected by the USB. The TH6503 translates all the data in the USB-specific format and generates the necessary control signals. The TH6503 requires a minimum number of external elements and can easily be implemented in a circuitry. It provides an external clock which can be used to activate a microcontroller.
Rev. 3.5 Dec 2000
TH6503 USB Low-Speed Interface
Function
USB Data Transmission
The TH6503 supports the USB Specification 1.1 data model. Data from the USB host to the device and vice versa is transmitted serially. The data are NRZI coded to increase transmission reliability; bit stuffing (inserting an extra 0 bit after any 6 consecutive 1 bits) is performed and a CRC check carried out. Bit stuffing, NRZI coding/decoding and CRC checks or generation are performed within the TH6503. The data is transmitted in packets. Three types of packets are defined for the USB: token, data and handshake. The token is always passed on by the host. It contains a PID (packet identifier) which defines the direction of the following data transmission and the address of the device and endpoints to be addressed. Depending on the previous token command, data is transferred from the USB host to the TH6503 (OUT transfer) or transferred from the TH6503 to the USB host (IN transfer). In the process the respective FIFOs are written (OUT) or read (IN). The data transfer is concluded with a handshake. If the data has been received successfully, an ACK is sent to the data source. If no data is ready for an IN transfer out of the TH6503, it sends an NAK handshake instead of the data (if endpoint is enabled).
TH6503/ Microcontroller Cooperation
to USB Hub/Host
TH6503
Endpoint 2 USB Interface
Interrupt Transfer serial Data Vendor specific Data
Endpoint 1
Control Transfer
Microcontroller
Input Device
Endpoint 0
Figure 2. Data Flow The TH6503 is responsible for the data flow between the USB and the microcontroller. It ensures that the USB transfers the data in line with the protocol. All information in the protocol layer is decoded by the TH6503 and carried out accordingly. The data arriving from the USB host is stored in a FIFO buffer until it is collected by the microcontroller. Data transmitted to the USB host are imported from a FIFO buffer which has previously been filled by the microcontroller. A /INT signal signals to the microcontroller that the FIFO status has been changed by USB. Data is transferred between the microcontroller and the TH6503 via a software-emulating serial interface controlled by the microcontroller. As the TH6503 cannot interpret the content of the data, it must be evaluated within the microcontroller. This also applies to USB-specific control information. All USB-typical descriptors and the associated requests must be created and managed by the microcontroller. The setting of the USB address serves here as an example. After resetting the USB, the address is set to the default value 0 (USBAddressRegister). A specific address is transferred from the USB host software to the device with the SET_ADDRESS command. This command, like all SET and GET commands, can only be decoded by the microcontroller. The USB address is decoded in the TH6503 with the aid of the USB AddressRegister. For this reason the microcontroller must write the USB address determined in this register. The TH6503 supports the USB suspend mode. Control takes place via the microcontroller. The ACT bit can be used in the StatusRegister <5> which is set on the USB for each activity. If this bit has been inactive for a longer period of time (3 ms), the microcontroller can set the TH6503 and itself in the suspend mode using the SUS bit in the BridgeConfigRegister <4>. The suspend mode can be ended using the software or an external signal. Apart from the suspend mode, the TH6503 also supports a number of other power saving modes which either stop the microcontroller by switching off the clock or set the whole USB bridge in a power saving mode. The TH6503 provides the clock pulse for the microcontroller. It can be programmed with the OCR 1 - OCR 0 bits in the BridgeConfigRegister <1-0>. The TH6503 supplies 3.3V voltage to power the microcontroller; this is produced by the adjacent 5V bus power supply connection.
2
TH6503 USB Low-Speed Interface
TH6503/ Microcontroller Cooperation (continued)
VBus GND
1 5
Power Supply 3.3V Status Signals
SIE
V3.3
2
10
Serial Interface Engine
Control Signals
1k5
Microcontroller Interface
13 12 11 10
SCK SIN SDI SDO
DD+
3 4
USB I/O
Bus Interface
14 /ORST
Oscillator/ Divider
6 7 8
WAKE
15 OCLK
16
RESET V3.3
Figure 3. TH6503 Block Diagram
Microcontroller Interface
The data is transferred between the microcontroller and the USB bridge using the clock (SCK) generated by the microcontroller asynchronous to the USB clock.
Data IN Transfer
(from the microcontroller to the TH6503) Data IN transfer is initiated with rising SIN edge (IN packet sync). Data is transferred via the SDI pin. Initially the Adr/CntInRegister which indicates the internal address in the TH6503 is written. Data is subsequently transferred beginning with byte 0 to Byte n LSB first. Bits IC3-IC0 in the Adr/CntInRegister <3-0> contain the information on the number of bytes to be transferred to the USB host if the target of the data transfer was an IN FIFO. A zero data transfer is identified with reset of IC3IC0 bits after writing the Adr/CntInRegister one additional clock on SCK must be generated. If a register is the target of the data IN transfer the bits IC3-IC0 and TI have no meaning. With falling SCK edge the microcontroller transmit the bits to SDI and the bits are imported from the bridge with increasing SCK edge. After each transmission of 8 bits the respective IN FIFO value is increased by 1. If the microcontroller writes more data than indicated in the Adr/CntInRegister, the oldest data are overwritten. After the final falling edge of SCK first SDI and then SIN must be reset to 0 to terminate the transfer. The associated IN Done bit in the StatusRegister is reset automatically to enable USB IN transfer.
3
TH6503 USB Low-Speed Interface
Microcontroller Interface (continued)
1
Bridge latches Data on rising edge of SCK
Microcontroller shifts Data on falling edge of SCK
SCK
0 1
0
1
7
n+8
SIN
0 End of IN Transfer 1
SDO
0 1
/INT
SDI
0
AC0
AC1
AC2
AC7
Data Bit 0
Bit n
Microcontroller outputs Adr/CntInRegister Bit 0 / AC0 on SDI
Figure 4. Serial Data IN
Data OUT Transfer
(from the TH6503 to the microcontroller) An impulse on the SDI link at SIN = 0 represents the OUT packet sync for an OUT transfer. With the falling SCK edge the data (LSB first) is shifted to SDO and with rising SCK edge accepted by the microcontroller. The StatusRegister is transferred initially followed by the CntOutRegister and finally the OUT FIFO data. If the transfer is terminated after less than 8 clock pulses, only single StatusRegister bits are read. Linear transfer is interrupted by SIN = 1 and must be initiated with a new OUT packet sync at SIN = 0. Two impulses on the SDI link initiate a transfer of the CntOutRegisters and of the following OUT FIFO bytes without the StatusRegister. A zero data transfer is identified by an OUT Count Byte value of 0. The end of a Data OUT transfer clears the SET bit in the CntOutRegister and the OD bit in the StatusRegister to make the next USB OUT or Setup transfer possible.
Microcontroller latches Data on rising edge of SCK 1
Bridge shifts Data on falling edge of SCK
End of Transfer n
SCK
0 1
0
1
SIN
0 1
any break after identify the /INT source possible
SDO
0
Status0
Status1
Status2
Status n
/INT
Clear Interrupt Latch 1 n <= 7
SDI
0
SDI pulse with SIN=0: - copy StatusRegister to Shift Register for Serial Data Out
Figure 5. OUT Transfer of StatusRegister
4
TH6503 USB Low-Speed Interface
Microcontroller Interface (continued)
1
Microcontroller latches Data on rising edge of SCK
Bridge shifts Data on falling edge of SCK
End of OUT Transfer (OUT Tranfer after reading the Status -and CntOutRegister with SIN=0 clears EP0 Out Done 7 15 n+16
SCK
0 1
0
1
SIN
0 1
Bridge outputs next Register (CntOutRegister) Bit 0 on SDO
SDO
0
Status0
Status1
Status2
Status7
CNT0
CNT7 FIFO Bit 0
Bit n
/INT
Clear Interrupt Latch 1
SDI
0
SDI pulse with SIN=0: - transfer StatusRegister to Serial Data Out
Figure 6. Complete Data OUT Transfer
Microcontroller latches Data on rising edge of SCK 1
Bridge shifts Data on falling edge of SCK
End of OUT Transfer (OUT Tranfer > 8 clocks the Status -and CntOutRegister with SIN=0 clears EP0 Out Done 7 n+8
SCK
0 1
0
SIN
0 1
Bridge outputs next Register (FIFO) Bit 0 on SDO
SDO
0 1
CNT0
CNT1
CNT7
FIFO Bit 0
Bit n
/INT
SDI
0
Two SDI pulses with SIN=0: - transfer CntOutRegister and OUT FIFO Bytes to Serial Data Out
Figure 7. OUT Transfer, only CntOutRegister and OUT FIFO Bytes
Interrupt Function
If SIN = 1, the SDO pin can be used to generate an interrupt signal. The interrupt is low active. It is triggered if a control transfer is made from the USB host or a control or interrupt transfer is made to the USB host and one of the ID12, ID0 or OD bits has been set in the StatusRegister <3-1> or at high level of the WAKE pin. An interrupt signal is also triggered on RESUME and USB_RESET.
The interrupt latch is reset on reading the status register. If an interrupt is generated during reading StatusRegister, this interrupt is latched and the interrupt source is after new StatusRegister reading visible. A WAKE interrupt is only generated during the stop state (bits SO and/or SMC in the BridgeConfig Register are set).
5
TH6503 USB Low-Speed Interface
Timing Serial Interface
Figure 8 and Figure 9 show the timing of the serial interface of the TH6503. The serial interface is controlled by a standard microcontroller. It can be connected with any microcontroller port.
t3
SCK
t6 t4 t5 t7
SIN
t8 t9
SDO
t10 t11
/INT
SDI
Bit 0
Bit n
Figure 8. Timing Serial Data IN
t3
SCK
t16 t17 t4 t5 t13
SIN
t1 t2
SDO
t12 t15
Bit 0
Bit n
SDI
t14
Figure 9. Timing Serial Data OUT
6
TH6503 USB Low-Speed Interface
Timing Serial Interface (continued)
Description [1] General Oscillator Input period on OSC1 Rising time of SDO Falling time of SDO SCK period High time SCK [2] Low time SCK [2, 3] Data IN Setup time of SCK after rising edge of SIN Hold time of SIN after last rising edge of SCK Setup time of INT-Signal after rising edge of SIN Hold time of INT-Signal after falling edge of SIN Setup time of Data on SDI before rising edge of SCK Hold time of Data on SDI after falling edge of SCK Data OUT Setup time of SDI-pulse after falling edge of SIN Setup time of SIN after last falling edge of SCK High time of SDI-pulse Setup time of Data on SDO after falling edge of SDI-pulse Setup time of SCK after falling edge of SDI-pulse Setup time of Data on SDO after falling edge of SCK
Symbol
Unit
min
typ
max
ns t1 t2 t3 t4 t5 ns ns ns ns ns
164 20 7 600 345 255
170
Step
t6 t7 t8 t9 t10 t11
ns ns ns ns ns ns
170 170 200 165 170 0
t12 t13 t14 t15 t16 t17
ns ns ns ns ns ns
170 170 255 280 170 365
Notes: [1] Capacitive load of 50 pF [2] Can be asymmetrical [3] The low time of SCK between the last bit of a byte and the first bit of the next byte must be at least 510 ns.
Input signals are double buffered and digital filtered. Therefore all spikes with a width < 255 ns are suppressed.
7
TH6503 USB Low-Speed Interface
Connecting the TH6503 with a Microcontroller
The TH6503 can be connected with any microcontroller via a serial interface. The serial outputs can be connected with any microcontroller ports. The TH6503 out clock can be used to provide the clock pulse supply to the microcontroller. The
reset output is low active and configured in an open drain structure. For this reason the output must be set at a defined level with external V3.3 resistance.
TH6503
SCK SIN SDI SDO OCLK
13 12 11 10 15
MC6805
PA0 PA1 PA2 PA3 XOSC1 XOSC2 /RESET
TH6503
SCK SIN SDI SDO OCLK
13 12 11 10 15
Z86Kxx
P24 P25 P26 P27 XTAL1 XTAL2 /RESET
/ORST
14
/ORST
14
V3.3
Figure 10. The Connection between the TH6503 and the MC6805 by Motorola
V3.3
Figure 11. The Connection between the TH6503 and the Z86Kxx by Zilog
TH6503
SCK SIN SDI SDO OCLK
13 12 11 10 15
80C51
P1.0 P1.1 P1.2 P1.3 XTAL1 XTAL2 RST
TH6503
SCK SIN SDI SDO OCLK
13 12 11 10 15
PIC16C5x
RA0 RA1 RA2 RA3 OSC1 OSC2 /MCLR
/ORST
14
/ORST
14
V3.3
Figure 12. The Connection between the TH6503 and the 80C51 by Intel
V3.3
Figure 13. The Connection between the TH6503 and the PIC16C54 by Microchip
8
TH6503 USB Low-Speed Interface
Application Wiring Diagram
Figure 14 shows a sample Application circuitry with the TH6503 and a MC68HC05. To stabilize the internal power supply the V3.3 pin must always be connected with an 10 capacitor.
Figure 14. Sample Wiring diagram to connect the TH6503 with an MC68HC05
WAKE Function
The USB specification defines that a device has to go into suspend mode if no bus traffic was detected for ca. 3 ms. After the device is set to suspend mode, the WAKE pin can be used to Wake up the device with an external event. If the WAKE pin is connected with an RC-Element, the TH6503 wakes up after the time defined by the RC-Element. This feature can be used to check for data in periodical time frames.
RESET Output
The reset output (/ORST) of the TH6503 can be connected with the reset input of the microcontroller. It's a low active signal. This signal has a minimum length of 31 clock cycles with a default frequency of 1.5 MHz (see Pin Description for details). After this reset pulse the microcontroller can reseted but it must wait to programming the TH6503 until the USB reset is inactive. All register of TH6503 will be held in reset state, exept the StatusRegister, until the corresponding bits HWR or RES is cleared.
9
TH6503 USB Low-Speed Interface
Register Description
The StatusRegister, CntOutRegister and the OUT FIFO can only be read by the microcontroller. The internal Registers of the TH6503 can only be written by the microcontroller.
StatusRegister (read only)
always the first byte of a data out transfer is loaded in the out shift register with the falling edge of an pulse on SDI with SIN=0
Bit Number 7 Bit Mnemonic HWR Reset Status 1
Function Hardware Reset ? is set if the reset source is POR, RESET pin or low voltage reset ? is reset automatically on reading the StatusRegister and also by the following SW-Reset before reading the StatusRegister
6
RES
0
USB Reset ? is set so long as a reset is received on the USB (SW reset) ? is reset automatically on reading the StatusRegister and also by the following HW-Reset before reading the StatusRegister ? the reset of this bit enables EP0 Out and EP0 In (EO0 and EI0 bits in the SerialFlag Register are set)
5
ACT
0 ? ? ? ?
USB Activity is set when the USB is active (all bus states exept IDLE) is reset automatically on reading the StatusRegister can be used by the microcontroller to calculate the suspend time if set the SO and SMC bits in the BridgeConfigRegister are reset USB Resume Detect ? is set automatically if a resume status has been decoded ? is reset automatically if the resume status has been terminated ? if set the SO and SMC bits in the BridgeConfigRegister are reset
4
RDT
0
3
ID12
0
EP1/2 IN Done ? is set if the data requested by an IN token have been completely transmitted to the USB host and an ACK has been received ? is reset with the falling SIN edge (end of IN transfer)
2
ID0
0
EP0 IN Done ? is set if data requested by an IN token have been completely transmitted to the USB host and an ACK has been received ? is reset with the falling SIN edge (end of IN transfer)
1
OD
0
OUT Done ? is set automatically if the data are complete in the FIFO after a valid SETUP or OUT token has been received and an ACK has been sent to the USB host ? is reset with the rising SIN edge (end of OUT transfer)
0
WA
1
WAKE Activity ? is set and reset automatically depending on the voltage level at the WAKE pin ? is an inverted copy of the WAKE pin and can be used as low active interrupt output, when SIN = 1
10
TH6503 USB Low-Speed Interface
Register Description (continued)
CntOutRegister (read only) second byte of each out transfer following an OUT packet sync
Bit Number 7-6 Bit Mnemonic OA Reset Status 0 Function OUT Address last valid OUT endpoint ? indicates the endpoint of actual OUT FIFO data 00 EP0 01 EP1 10 EP2 ? only valid if EP1 OUT or EP2 OUT enabled, otherwise the internal Revision number is visible 5 TO 0 Toggle OUT ? is set if the data packet PID was DATA1 and reset if the data packet PID was DATA0 ? is latched with a valid EP0 SETUP or a OUT Token 4 SET 0 Setup ? is set if a SETUP token is received ? is reset after OUT transfer to microcontroller ? no STALL or NAK is sent because it is not permitted on the SETUP token ? the SO0 and SI0 (STALL EP0) flags in the USBFlagRegister are reset on rising edge of Setup ? a SETUP token flash all IN FIFOs 3-0 OC3-0 0 EP0 OUT Byte Count amount of OUT data received in the EP0 FIFO in bytes ? applicable values from 0 to 8 ? a zero data transfer is identified 0
Internal Register
Adr/CntInRegister (write only) first byte of each data in transfer following the IN packet sync
Bit Number 7 Bit Mnemonic TI Reset Status 0 Function Toggle IN ? is set if the data packet PID is DATA1 and reset if the data packet PID is DATA0 6-4 RA2-0 0 Internal Address destination address for a write operation to a TH6503 register or IN FIIFO 3-0 IC3-0 0 IN Byte Count number of data bytes to be transmitted without Adr/CntInRegister from the microcontroller to the TH6503 if the destination address was an IN FIFO ? applicable values from 0 to 8 ? 0 indicates a zero data transfer to the USB host, but blocks the InFIFO until ACK is received
11
TH6503 USB Low-Speed Interface
Register Description (continued)
EP0/1/2 FIFO (write only) Internal Address: b000, b001 or b010 Size: * * * * * 8 bytes The device user data is stored temporarily at this location for transfer to the USB host. the address b000 indicates a data transfer from EP0 the address b001 indicates a data transfer from EP1 the address b010 indicates a data transfer from EP2 only one of the three addresses may be used at any one time; FIFO is used alternately, depending on the device function will be flushed with a new SETUP token for as long as bit SET in CntOutRegister is set
SerialFlagRegister (write only) Internal address: b100 Size: 8 bits All endpoints must remain deactivated until USB reset has been decoded (Statusregister <6>).
Bit Number 7-6 5
Bit Mnemonic X EO2
Reset Status 0 0
Function reserved - must be set to 0 Enable EP2 OUT activate endpoint 2 OUT ? Microcontroller can set the bit after detecting a USB reset in order to enable data transfers from the USB host via EP2 ? If set the CntOut Register bit <7-6> indicates the source of the last OUT transfer binary coded
4
EO1
0
Enable EP1 OUT activate endpoint 1 OUT ? Microcontroller can set the bit after detecting a USB reset in order to enable data transfers from the USB host via EP1 ? If set the CntOut Register bit <7-6> indicates the source of the last OUT transfer binary coded
3
EI2
0
Enable EP2 IN activate endpoint 2 IN ? Microcontroller can set the bit after detecting a USB reset in order to enable data transfers to the USB host via EP2
2
EI1
0
Enable EP1 IN activate endpoint 1 IN ? Microcontroller can set the bit after detecting a USB reset in order to enable data transfers to the USB host via EP1
1
EI0
0
Enable EP0 IN activate endpoint 0 (IN transfer) ? is set automatically after detecting a USB reset to enable IN control transfers to the USB host
0
EO0
0
Enable EP0 OUT activate endpoint 0 (OUT transfer) ? is set automatically after detecting a USB reset to enable OUT control transfers to the USB host
12
TH6503 USB Low-Speed Interface
Register Description (continued)
USBFlagRegister (write only) Internal address: b101 Size:
Bit Number 7
8 bits
Bit Mnemonic FI2 Reset Status 1 Function Flush EP2 IN clears EP2 FIFO ? is set and reset automatically depending on the actual FIFO Status ? must be set before EP2 of the EP1/2 FIFO can be overwritten by the microcontroller
6
FI1
1
Flush EP1 IN clears EP1 FIFO ? is set and reset automatically depending on the actual FIFO Status ? must be set before EP1 of the EP1/2 FIFO can be overwritten by the microcontroller
5
FI0
1
Flush EP0 IN clears EP0 FIFO ? is set and reset automatically depending on the actual FIFO Status ? must be set before the EP0 FIFO can be overwritten by the microcontroller
4
BO0
0
Busy OUT blocks the EP0 OUT FIFO for the USB host ? is set and reset automatically depending on the actual FIFO Status ? TH6503 responds with no handshake for a USB host SETUP token or with a NAK signal for an OUT token (NAK state) ? to leave the NAK state, the microcontroller does an OutFIFO read (the microcontroller rereads the last data)
3
SI2
0
STALL EP2 sets EP2 to STALL ? TH6503 responds with a STALL for a USB host IN or OUT token if address and EP2 have been decoded ? only operative if EP2 is active
2
SI1
0
STALL EP1 sets EP1 to STALL ? TH6503 responds with a STALL for a USB host IN or OUT token if address and EP1 have been decoded ? only operative if EP1 is active STALL EP0 IN sets EP0 IN to STALL ? TH6503 responds with a STALL for a USB host IN token if address and EP0 have been decoded ? will be cleared after SETUP token
1
SI0
0
0
SO0
0
STALL EP0 OUT sets EP0 OUT to STALL ? TH6503 responds with a STALL for a USB host OUT token if address and EP0 have been decoded ? STALL is inoperative for a SETUP token from the USB host ? SETUP clears STALL EP0 IN and STALL EP0 OUT bits
USBAddressRegister (write only) Internal address: b110 Size:
Bit Number 7 6-0
8 bits
Bit Mnemonic X AD6-0 Reset Status 0 0 Function reserved USB device address USB address entered by microcontroller ? zero after reset ? microcontroller must decode the address from descriptor data after a SETUP (SET_ADDRESS) token and write it in this register
13
TH6503 USB Low-Speed Interface
Register Description (continued)
BridgeConfigRegister (write only) Bits only take effect after the data IN transfer has been completed. Internal address: b111 Size :
Bit Number 6
8 bits
Bit Mnemonic OS Reset Status 0 Function OCLK Static ? is set and reset by microcontroller ? if set the OCLK pin drives a static level on the OCLK pin, this level depends on the SMC bit in the BridgeConfigRegister OS SMC OCLK Output 0 0 Clock, programmed by OCR<1-0> bits 0 1 0 1 0 0 1 1 1 ? can be used as ending stop state signal for an external microcontroller with own clock ? works like a low active interrupt
5
FR
0
Force Resume terminates suspend mode ? is set by microcontroller if data is sent from connected device ? the TH6503 signals a Resume to the USB host ? the timing (10-15 ms) of the Resume State must be done by microcontroller
4
SUS
0
Suspend sets the TH6503 in suspend mode ? should be set by the microcontroller if no bus traffic is detected for longer than 3 ms ? can be set and reset by microcontroller only
3
SO
0
Stop Oscillator stops the microcontroller and the USB bridge (the SMC bit is set automatically) ? is set by the microcontroller ? is reset by an external wake up signal, USB activity or reset
2
SMC
0
Stop Microcontroller Clock stops the microcontroller ? is set by the microcontroller ? is reset by an external wake up signal, USB activity or reset ? only affects the OCLK pin
1-0
OCR1-0
00
Out Clock Rate output frequency on the OCLK pin 0 0 1.5 MHz (default) 0 1 2.0 MHz 1 0 3.0 MHz 1 1 6.0 MHz, without guarantee of symmetry, it depends on the quality of the oscillation element
14
TH6503 USB Low-Speed Interface
Flowchart for Programming the TH6503
Main Program Figure 15 shows the main order of events of the USB specific part of firmware for the microcontroller. The bits located in the StatusRegister mark the event. Depending on these bits the firmware must branch.
Initialisation SCK=0;SIN=1; SDI=0
Yes
SDO=1
No
Read StatusRegister
Read CntOutRegister and OUT FIFO
Yes
OUT Done
Reaction (depends on the received Data)
No
Data to send ?
Yes
EP0 IN Done
Yes
Write next Control Byte(s) to IN FIFO
No
No
Data to send ?
Yes
EP1/2 IN Done
Yes
Write next Device Data to IN FIFO
No
Reset SUS Bit in the BridgeConfigRegister
Yes
Resume Detect
No
Reset Suspend Timer
Yes
USB Active
No
USB Reset
Yes
Figure 15. Flowchart for Main Program (using TH6503 in Interrupt mode)
15
TH6503 USB Low-Speed Interface
Flowchart for Programming the TH6503 (continued)
Reading the StatusRegister The Reading of the Status Register is the first action of the microcontroller. The TH6503 stores the information on what's happened on the USB in this Register
Read StatusRegister
SIN=0
generating a pulse on SDI
Generating a rising edge on SCK to save bit on SDO
Save SDO bit
more bits to read ?
Yes
Generating a falling edge on SCK to shift next bit to SDO
No
abort transfer with SIN=0
Figure 16. Reading the StatusRegister
16
TH6503 USB Low-Speed Interface
Flowchart for Programming the TH6503 (continued)
Reading the CntOutRegister and OUT FIFO If the Out Done bit in the StatusRegister is set, the microcontroller must receive the data collected from the OUT FIFO.
Read CntOutRegister and OUT FIFO
continue after reading StatusRegister (see Fig.6 and Fig 7 on page 5)
generating a rising edge on SCK
save SDO bit
more bits to read ?
Yes
Generating a falling edge on SCK to shift the next bit to SDO
No
abort transfer with SIN = 1
Figure 17. Reading the CntOutRegister and OUT FIFO
17
TH6503 USB Low-Speed Interface
Flowchart for Programming the TH6503 (continued)
Reaction on the FIFO data After the microcontroller has collected the FIFO data, the microcontroller must decode the FIFO data and reacts appropriately.
Reaction
Setup bit = 1 ?
Yes
Decoding FIFO Data, Reaction depends on the request (see USB Spec Rev. 1.1, Chapter 9)
Figure 18. Reaction on the received Data
18
TH6503 USB Low-Speed Interface
Flowchart for Programming the TH6503 (continued)
Write next Device Data to TH6503 If IN FIFO data has to be sent to the USB host the microcontroller must wait until the corresponding IN DONE bit is set (IN FIFO is empty). Then the microcontroller can store the next data in the IN FIFO.
Write Adr/CntInRegister
Write Internal Register
Write next Control Byte(s) to IN FIFO 0
Write next Device Data to IN FIFO 1 or 2
SIN=1
output first bit on SDI
generating a rising edge on SCK to latch bit by bridge
more bits to write ?
Yes
generating a falling edge on SCK and output the next bit on SDI
No
End of IN Transfer SIN=0 and SCK=0
Figure 19. Writing next Device or Control Data to IN FIFO
19
TH6503 USB Low-Speed Interface
Electrical Characteristics
All voltage values are referenced to GND (GND = 0 V). All values are based on the USB specification V1.1. If any value is unspecified, the value from the USB specification V1.1 is valid. Absolute maximum ratings
Parameter DC supply voltage Input voltage Input Current Storage temperature range (ceramic) Storage temperature range (plastic) Power Dissipation (SOP16) Symbol VDD VIN I IN TSTGC TSTGP PD Min - 0.3 - 0.3 - 10 - 65 - 40 Max 7.0 V3.3 + 0.3 10 150 125 600 Unit V V mA C C mW
Recommended Operational Conditions
Parameter DC supply voltage Operating temperature range Junction temperature Operating Frequency Symbol VDD TA TJ fOP 6.00 Min 4.40 0 Typ 5.00 Max 5.25 70 < 150 Unit V C C MHz
20
TH6503 USB Low-Speed Interface
Electrical Characteristics
Static Characteristics
Parameter Power supply voltage Power supply current Stand-by Current [5] Voltage input LOW Voltage input HIGH Schmitt trigger, positive going threshold Schmitt trigger, negative going threshold Hysteresis, Schmitt trigger (VT+ - VT-) Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Single Ended Receiver Hysteresis Input low current Input with pullup Input high current Input with pulldown Voltage output LOW Voltage output HIGH Current Output Differential output LOW Differential output HIGH Hi-Z Output Leakage Current Symbol V 3.3 I3.3 ISTB V ILCMOS V IHCMOS V T+CMOS V T-CMOS V HYSCMOS V DI V CM V SE V HYSE IIL IILU IIH IIHD V OL V OH IO VOLD V OHD IOZ RL of 15 KOhm to GND RL of 1.5 KOhm to 3.6 V V IN = GND or V3.3 2.8 -10 V IN = GND V IN = GND V IN = V3.3 V IN = V3.3 IOL = 1 mA IOH = 1 mA 2.4 1 0.3 3.6 10 V IL to VIH,V IH to VIL |(D+)-(D-)| Includes VDI 0.8 0.5 0.2 0.8 0.8 0.1 -10 -50 -10 7 22.9 -21.0 10 -7 10 65 0.4 2.5 2.0 0.7*V 3.3 2.4 80 Condition [4] Min 3.00 Typ 3.30 Max 3.60 60 150 0.3*V 3.3 Unit V mA A V V V V V V V V V A A A A V V mA V V A
Notes: [4] Specified at VDD = VBUS = 4.40V to 5.25V and tested at room temperature only [5] Differential Transceiver fs in Suspend Mode, tested without pull-down and pullup Resistors on the D- and D+ data line
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TH6503 USB Low-Speed Interface
Pin Description
Pin Description USB Interface 1 5 4 3 VBus GND D+ DI I I/O I/O adjacent 5V bus voltage Ground USB data USB data ? must be connected via 1.5 kOhm resistor to 3.3 V for low speed devices Microcontroller Interface 13 SCK I Serial Clock (generated by microcontroller) ? OUT transfer: SDO is accepted by the microcontroller in high status or with falling SCK edge. The USB bridge shifts the next bit to SDO in low status or with rising edge. ? IN Transfer: SDI is accepted by the USB bridge in high status or with falling SCK edge. ? The microcontroller shifts the next bit to SDI in low status or with rising edge. ? internal pulldown 12 SIN I Serial Input Direction (generated by the microcontroller) ? specifies the direction of the data transfer and marks the end of a FIFO transfer ? SIN = 0: data is sent from the USB bridge to the microcontroller via SDO. An OUT packet sync for the StatusRegister or CntOutRegister can be triggered via SDI. A rising edge terminates a Status or OUT transfer and the USB OUT Done status bit is cleared. ? SIN = 1: Data is sent from the microcontroller to the USB bridge via SDI. SDO emits an /INT signal. A falling edge terminates an IN transfer and the EP0 IN Done or EP1/2 IN Done status bit is cleared if the destination address is a FIFO address. ? rising edge indicates the commencement of an IN transfer (IN packet sync). The IN is started once SCK is pulsed. The Adr/CntInRegister is transferred initially. ? internal pulldown 11 SDI I Serial Data IN (from the microcontroller to the USB bridge) ? generated by the microcontroller ? SIN = 0: the falling edge from a single SDI impulse loads the first bit (LSB first) of the StatusRegisters to SDO. The StatusRegister can be read. Two SDI impulses load the first bit of the CntOutRegister. ? SIN = 1: SDI transfers the serial data. ? internal pulldown 10 SDO O Serial Data Out (from the USB bridge to the microcontroller) ? generated by the USB bridge ? SIN = 0: SDO show the Status of bit 0 of the StatusRegister (WA) and after a SDI pulse SDO transfers the serial data. ? SIN = 1: SDO is used to generate the /INT signal which can be used to control the microcontroller interrupt ? /INT: - Low active signal to SDO at SIN 1 - is a NOR connection of the RESUME signal, USB reset and an interrupt latch - Interrupt latch is set for all increases in OUTDone, EP0 IN Done and EP1/2 IN Done edge. - Interrupt latch is reset, if the StatusRegister is read (SDI impulse at SIN= 0). 15 14 OCLK /ORST O Clock out for microcontroller (programmable frequency)
open Reset Out (HW- or SW reset) drain ? ? ? ? ? ? ORST=0 reset state ORST=1 normal operation must be connected with an external pullup resistor (to V3.3) all resets are indicated on this pin this type of reset can be determined by evaluating the bits HWR or RES in the StatusRegister <7> or <6> Reset conditions: - internal POR - RESET pin - min. 20s (31 OCLK cycles at 1.5 MHz) or as long as the RESET pin is active - Low voltage reset if VBUS<3.3V 10% with a minimum of 20 s (31 OCLK cycles at 1.5 MHz) or as long as VBUS < 3.3V - USB-Reset - reduced to 20 s (31 OCLK cycles at 1.5 MHz), the end of a USB reset is indicated by a rising edge of /INT and by cleared RES bit in the StatusRegister
Miscellaneous 6 7 OSC1 OSC2 I O Oscillator In for a quartz, ceramic resonator or external clock input, 6 MHz 1.5% Oscillator Out ? if a specific high trigger level is reached (Schmitt Trigger Characteristic) the USB bridge oscillator is restarted and ? the SO and SMC bit in the BridgeConfigRegister is cleared. ? it may be connected to an RC element to achieve restart cycles from 50 to 100 ms ? the input signal is compatible with large slew rate if the SO or SMC bit in the BridgeConfigRegister is set a rising edge on the WAKE pin generates an interrupt signal on SDO, when SIN = 0 RESET input with Schmitt-Trigger characteristic (internal pullup) 3.3 V output must be connected with an external capacitor (approx. 10) ? Test pin, internal pulled up (do not connect to external circuitry)
8
WAKE
I
16 2 9
/RESET V3.3 TEST
I O I
22
TH6503 USB Low-Speed Interface
Pinout Information (Top View)
VBUS 1 V3.3 2 D- 3 D+ 4 GND 5 OSC1 6 OSC2 7 WAKE 8
16 RESET 15 OCLK 14 /ORST
TH6503
13 SCK 12 SIN 11 SDI 10 SDO 9 TEST
Package Information (SOP 16 WB)
The TH6503 is available in a SOP 16 WB Package.
E
H
123 D
A1 e b
A L
?
Small Outline Package (SOP) SOP 16 Wide Body (WB) Package type SOP WB 16 min max D 0.398 0.413 E 0.283 0.300 H 0.393 0.419 A 0.091 0.111 A1 0.002 0.014 e 0.05 b 0.013 0.020 L 0.012 0.050 ? 10 Package code DF16
Dimensions in inches, coplanarity < 0.004", original dimension: inch SOP WB 16 min max 10.11 10.49 7.19 7.62 9.98 10.64 2.31 2.82 0.05 0.36 1.27 0.33 0.51 0.30 1.27 10 DF16
Dimensions in millimeters, coplanarity < 0.1 mm, original dimension: inch
Ordering Information Quality Data
The TH6503 USB Low-Speed Interface is available in a 16 pin SOP WB package. The order number is TH6503. Quality data is available on request. Contact: Thesys Mikroelektronik Produkte GmbH Quality Assurance Haarbergstr. 67, 99097 Erfurt, Germany Tel.: +49-361-4276155, Fax: +49-361-4276060
23
TH6503 USB Low-Speed Interface
Worlwide Sales Offices
For the latest version of this document, Go to our website at:
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www.melexis.com
Or for additional information
Contact Melexis Direct:
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USA
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United Kingdom
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Important Notice
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis' rendering of technical or other services. (c) 1998 Melexis GmbH. All rights reserved.
10LT.155E
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